IPextreme Blog

iTunes comes to IP

Those of you following me on Twitter (@warren_savage, and @ipextreme) may have noticed from my tweets in recent weeks that something big is happening.

Today we are introducing Xena, a cloud-based platform that enables semiconductor companies and IP companies to manage their IP and IP business. You can visit our web site (www.ip-extreme.com) for more details about that, but what gets me excited about this is the prospect of enabling the kind of infrastructure the IP industry has lacked for all of its 15 years of existence.

Historically, most IP providers have delivered IP via FTP and supported customers via email and telephone. Most IP creators within semiconductor companies have relied on adhoc techniques for packaging and sharing their internally created IP and controlling access to externally purchased IP. The larger the company, the better and more sophisticated the techniques put in place to manage this. But smaller companies can never really afford to invest in these things. 

I find the analogy not dissimilar to the music industry of the past where it was basically impossible for emerging artists to get a foothold in the industry without a record label to provide the funds to subsidize the making of a record and paying for the marketing and concert tour that would sell records.  Without that infrastructure the artist was at a significant disadvantage regardless of their talent.

That all changed with the digital age and the invention of MP3’s. But having the music in digital form was only the first step. By having the music in digital format, it allowed the musicians to ride the wave of Moore’s law—increasing capability at reduced cost by making a whole variety of inexpensive digital music equipment available to musicians allowing them to self-produce their work at an affordable cost. 

The next step of the evolution of the music industry was enabled by the internet to allow music to be exchanged. In this era, companies like Napster came into being to allow music to be shared (illegally), but that didn’t help the musician because they couldn’t control the access and therefore couldn’t effectively monetize their work. 

The final piece of the evolution was the creation of the iPod/iTunes franchise by Apple. At last, there was an infrastructure that took advantage of all the power of technology and put it together in a platform that finally connected IP creators (musicians) to the IP users (listeners). That successful model has changed the world and still offers lessons today for its application in other fields. I think one of those is semiconductor IP.

While it is certainly a stretch that Xena might have an impact on the IP industry the way that iTunes had on the music industry, it’s great to be part of something that can similarly connect IP creators to IP users. With Xena we are able to share the technology we have developed at IPextreme over the last 7+ years in running our global IP business with other companies that can benefit equally from our investment.  And with the cloud—it’s extraordinarily cost-efficient and scalable for all companies to now have a professional class infrastructure for running their companies in the age of the cloud.

If you are interested in what a Xena installation looks like, you can easily visit xena.ip-extreme.com and login as a guest user (free—of course!)

 

It's not a Sprint, its a Marathon

It’s that time of the year when the EDA industry puts on its annual show at the Design Automation Conference (DAC). This year’s DAC was held in San Diego, California from June 6-8, 2011. Like many of us involved in the semiconductor industry, going to DAC provides a once-a-year opportunity for us to reconnect with colleagues, customers, and partners from all over the world in a very efficient way.

This year’s DAC was a bit special for me.  When registering for the conference and looking for hotels, I noticed on the front page of the DAC website a promotion of the San Diego Rock and Roll Marathon, one of a series of running events held all over North America throughout the year. This year, the San Diego event was being held the day before DAC, Sunday June 5^th.  Being a lifelong runner, but never before competing in a marathon, this seemed like the perfect opportunity for me to give it a try.  So I did, along with a number of other sleepy-eyed DAC attendees seen in this picture taken at the Marriot hotel at 4:30am, 90 minutes before the start of the race where we joined with another 32,500 runners.

Please see the rest of the post by visiting the Electronics Weekly web site:

http://www.electronicsweekly.com/Articles/2011/06/27/51339/warren-savage-on-its-not-a-sprint-its-a-marathon.htm

 

The Geometry of EDA 360

Refreshingly honest. That’s probably my biggest takeaway I had from a broad-ranging conversation I had recently with John Bruggeman, Chief Marketing Officer at Cadence. It’s been nearly a year since Cadence had announced the EDA 360 vision and I was particularly interested to hear John’s thoughts on its affect on the industry and Cadence so far.

Consistent with the thoughts I’ve written about in this column over the last few years, John described the genesis of EDA 360 as being driven by the disruptive nature of Apple’s iPhone. That product-- more than any other in modern history, has changed the rules of the game for everyone in the electronics business. John went even further stating “That device changed and will continue to impact and change every consumer device that gets built” and the expectation by the users of those devices who can personalize them to their own needs has “forever changed and will never go back.”

But the question is what’s the EDA 360 vision got to do with Cadence and why is this man so excited about it?

Please see the rest of the post by visiting the Electronics Weekly web site:

http://www.electronicsweekly.com/Articles/2011/01/17/50288/warren-savage-on-the-geometry-of-eda-360.htm

The Other Side of the Rabbit Hole

2010 is shaping up to be a spectacular year for semiconductors. Gartner says the semiconductor market has rallied and should reach a record $300.3B in 2010, up 31.5% from 2009. This reflects more than $70B increase in revenue in a single year - a record jump for the semiconductor industry.

Please see the rest of the article on ElectronicsWeekly.Com

http://www.electronicsweekly.com/Articles/2010/12/16/50124/warren-savage-on-the-other-side-of-the-rabbit-hole.htm

 

The Power of Information

I have never been one of those people frozen to make decisions because of the lack of enough data to make a “safe” choice. I’ve come to trust intuition and experience as important allies when faced with dealing with the unknown. In fact I’ve seen the ability to be comfortable with certain kinds of ambiguity as a key trait in good organizational leadership. As one raises through the ranks of management, the higher one goes, the more comfortable one needs to become with the unknown in order to lead others through the wilderness of situations where no one has gone before.

Check out the rest article on the EW site, and give me your thoughts here!

http://www.electronicsweekly.com/Articles/2010/07/06/48974/warren-savage-on-the-power-of-information.htm

Complex Electronic Systems-- Unsafe at Any Speed?

I wrote an article over the weekend for my column at Electronics Weekly regarding the exploding verification problems as electronic systems get more and more complex.  I resurrected Ralph Nader's premise about the automotive industry designing cars to be unsafe as a historical analogy to the dangers that exist in complex electronically managed systems today-- i.e.  automobiles.

 

Check out the article on the EW site, and give me your thoughts here!

 

http://www.electronicsweekly.com/Articles/2010/04/26/48485/warren-savage-on-still-unsafe-at-any-speed.htm

 

 

Great Day at the Constellations Conference

No April Fool. That was one cool event. If you missed it (perhaps because you were feeling too SNUG wherever you were), then be sure to sign up for the next one.

What am I talking about? Yesterday's IPextreme Constellations Conference at the TechMart in Santa Clara.

Why was it so cool? For one thing, it was fast-paced, informal, interactive, and fun. Really - and I am talking about a roomful of engineers discussing semiconductor IP - we had a good time.

But most of all it was informative. Representatives from each of the 10 companies in the Constellations program took turns presenting their product offerings - clearly and succinctly. No marketing mumbo-jumbo, no over-the-head obfuscating technical jargon. Each presenter clearly stated in everyday terminology what chip design challenge his company was tasked with solving and how his product(s) solved that problem.

Kudos to all the presenters - you all did a great job!

The result of that will certainly be an even better sharing of resources between the Constellations members - "No, we don't have IP for that problem, but I know who does." I think all member companies left the event with a stronger understanding of each others product offerings and the confidence that behind those products are a bunch of really smart people who know their customers' needs and are committed to their customers' success.

Things really got going at the afternoon technical panel discussion. The theme of the event was Trusting your IP Provider and few provocative questions from moderator Ron Wilson of EDN spurred some highly-charged comments from the IP consumers in the audience - challenging the panel on the topic of trust, from perspectives of both technical competency and ethical behavior. (These IP consumers were either doing really good role-play or did indeed have some truly challenging experiences with purchased IP.)

The panel responded to a series of what-if scenarios smartly and convincingly, clearly demonstrating their preparedness and commitment to supporting their IP users. Stories from both the panel and the audience involving both good and bad behavior on the part of both IP providers and IP consumers demonstrated that building trust is a two-way street requiring openness and honesty on both sides. At the end of the discussion, all agreed that the only way IP integration works is when the provider and integrator are committed to the project's success and, of course, open and honest when it comes to dealing with unexpected challenges.

The day concluded with a demo of technology interoperability involving products from a combination of Constellations companies. All-in-all it was a fun day away from the office and another step forward for the IP industry.

Myth Busted: IEEE 1149.7 does not replace IEEE 1149.1

If you've been hesitant to add IEEE 1149.7 capabilities to your next chip because you believe it means abandoning your previous investment and experience in IEEE 1149.1, you're not alone. The notion that IEEE 1149.7 replaces IEEE 1149.1 is a myth (or, more to the point, a bit of misinformation) that has managed to spread itself around. The true story has a much happier ending.

IEEE 1149.7 (also known as compact JTAG or cJTAG) offers several benefits over traditional IEEE 1149.1 (JTAG), but it does not require you to change your existing on-chip JTAG infrastructure. On the contrary; IEEE 1149.7 simply provides new and better ways to take advantage of your existing IEEE 1149.1 on-chip test logic.

All you have to do is insert the cJTAG-IEEE 1149.7 IP from IPextreme between your existing IEEE 1149.1 TAP Controller and your chip's JTAG I/O pins and your chip is cJTAG-enabled.

And what does that mean?

Well, for one thing, your on-chip JTAG functions (IEEE 1149.1 boundary scan and/or application-specific test/debug strategies) will work as they did before; the presence of the cJTAG IP is transparent to your on-chip IEEE 1149.1 TAP Controller. So, there is no need to re-design your on-chip test logic. And, when operating in an IEEE 1149.1 series scan environment, the cJTAG IP is transparent to both the tester and the on-chip test logic.

Beyond that, usage of the added IEEE 1149.7 capabilities depends on the external environment: the capabilities test/debug hardware and software, the capabilities of other devices on the scan chain, and how the devices are connected together. Here are a few examples of the capabilities that you gain with a cJTAG-enabled chip:

• The ability to operate in a star topology: Chips connected in parallel means a shorter path to the chip of interest. And that means faster scan operations. Device selection occurs between the cJTAG IP and the tester. Your on-chip IEEE 1149.1 TAP Controller sees only a direct connection to the tester.
• Shorter series scan paths: In a series topology, you can reduce the length of your series scan path by using the IEEE 1149.7 Super-Bypass feature. With Super-Bypass activated, the cJTAG IP provides 1-bit IR and DR scan paths, bypassing your IEEE 1149.1 TAP Controller. Again, there is no need to change to your existing on-chip IEEE 1149.1 test infrastructure - it is simply bypassed when it is not the target of a series scan operation.
• The option to use fewer chip-level test pins: The cJTAG IP can use either a 4-pin or 2-pin interface to the tester. When operating in 2-pin mode, the cJTAG IP continues to present the traditional 4-pin (TCK, TMS, TDI, TDO) JTAG interface to the on-chip TAP Controller while communicating with the tester using only TCK and TMS (or, more correctly, TCKC and TMSC in the IEEE 1149.7 2-pin nomenclature). If your device uses nTRST, there's more good news. The cJTAG IP can accept IEEE 1149.7 reset signalling through the 2-pin interface and send your on-chip IEEE 1149.1 TAP Controller a good old-fashioned nTRST pulse; so you no longer need a chip-level nTRST pin.

Other IEEE 1149.7 optional features like test logic power management, reset of functional logic, and data channel operation also require no changes to your on-chip IEEE 1149.1 TAP logic. Instead, the cJTAG IP uses "sideband" signals to interface to the associated on-chip clients.

So what's the point?

Taking advantage of IEEE 1149.7 features such as star topologies and 2-pin operation involves two distinct activities:
(a) Adding IEEE 1149.7 capabilities to your chip
(b) Developing a system-level test/debug solution that uses those capabilities

With the cJTAG IP from IPextreme, activity (a) is really just a simple integration task. For a few on-chip signal connections and about 2500 gates, your IEEE 1149.1 enabled chip becomes IEEE 1149.7 enabled. There is no need to re-work your existing IEEE 1149.1 on-chip test logic. And the chip will continue to work as before in an IEEE 1149.1 test environment.

Activity (b) is a system-level test/debug task for which you will need an IEEE 1149.7 capable test platform and, for example, to create star topologies, other IEEE 1149.7 capable devices. With the CJTAG IP integrated into the chip, you will be able to take advantage of the growing availability of IEEE 1149.7 capable devices and test/debug platforms.

CJTAG -- Not your Father's JTAG

Practically the entire electronics world is familiar with the venerable JTAG, or IEEE 1149.1 standard.  It was developed during an era when disco music and CB radios were fading from the scene and the age of microelectronics was dawning. In the early 1980's most electronics assemblies consisted of multilayer circuit boards with through-hole, dual in-line package (DIP) devices that were soldered into place. Testing was performed by means of "bed of nails" testers that placed a tester node on each net of the circuit board.

The first wave of miniaturization was in the form of surface mount technology (SMT) packages which were soldered on both sides of the board, prohibiting the bed-of-nails approach for direct testing. Test engineers scratched their head at how to get access to all the test points without physical access. Semiconductor companies banded together to form a joint test action group to study this problem and devise a solution. The solution they eventually arrived at became familiarly known as JTAG, and formally known as 1149.1 after ratification of the approach as an IEEE standard.

JTAG was simple.  Based on an easy to understand 4-bit state machine, every engineering student since 1985 could code up a JTAG controller for an interview test.  As an IEEE standard, it became ubiquitous and a feature on every chip to allow board testing in ever shrinking and congested boards. Over the years, clever engineers figured new and creative ways to use the JTAG standard for purposes other than board test.   For example, it became the defacto interface for chip level debug and for connecting the trace interfaces of microprocessors to debuggers.  This made a lot of sense because JTAG was expensive for chips in that it cost 4-5 pins.  Over time JTAG became even more overloaded by adding "side band" signals to allow for functions that could not be incorporated in standard JTAG protocol which caused the IEEE standard aspects of JTAG to be weakened.

The electronics community has been busily working for the last few years under the wraps of a new 1149 working group to modernize JTAG into a new standard-- 1149.7, or informally known as CJTAG (compact JTAG).

 

CJTAG is a major step improvement to the original standard, preserving all the functionality of original JTAG standard and extending it to cover all the current test, debug, and trace capabilities while reducing the pin count to 2 and making changes to the protocol to allow new capabilities to be added without the need for adding non-standard side-band signals.

For those of you interested in reading more about CJTAG, there are a lot of web resources available for you:

• The IEEE news release and access to the standard can be found here
• Information from TI about 1149.7 in their products can be found here
• Information about debug and test equipment from Lauterbach and Sophia Systems
• Information about verification IP from Globetech here

and last but not least

• Information about IP cores co-developed with TI and available from IPextreme can be be found here

The whole semiconductor industry is looking forward to extending the legacy of JTAG another 25 years.  

The Naught Decade

About a year ago, as the world was hurtling into depression, I remarked that that our semiconductor industry was entering a rabbit hole and like Alice in the Through the Looking Glass we might find it hard to imagine what’s on the other side. As we enter this new decade I believe we are emerging from the rabbit hole, and indeed we find our new reality “curiouser and curiouser!”

 

It’s been an astonishingly bad decade. As we entered it in late 1999 the entire world was drunk with dot-com irrationalism and fretting about Y2K. Those days now seem surreal as our memories are scarred by the dot-com crash, 9-11, the Enron scandal, US dollar collapse, war in Iraq, housing collapse, banking collapse, and stock market collapse. And that’s just in America! In the middle of all this are the two largest recessions in the history of the 50-year old semiconductor that bracket the beginning and end of the decade. A rough ride to say the least.

The rest of this post can be seen as part of my regular column on Electronics Weekly, at the following link:  http://www.electronicsweekly.com/Articles/2010/01/12/47767/warren-savage-on-the-naught-decade.htm