The pervasiveness of intellectual property (IP) based design is driving new processes within semiconductor companies that relate directly to IP issues at the SoC level. One of these is the IP design review, which is an important step in the tapeout process, intended to ensure that the IP present in the chip is as expected. With the advent of IP Fingerprinting through the Core Store, new tools have become available to the IP manager to reduce some of the risks associated with IP reuse.
IP fingerprinting? What’s that? you might ask. Simply put, IP Fingerprinting is a technology that allows the detection of third-party and internal IP in SoC designs. As illustrated in the diagram below, using fingerprinting technology involves three steps:
- Fingerprinting all IP products contained in databases within the company using a free IP Fingerprinting app from the Core Store
- Fingerprinting the SoC using the same app
- Analyzing the SoC fingerprint using Chip DNA Analysis software that searches a repository of IP fingerprints, looking for evidence of IP in the SoC
For the scope of this article, we will not get into the intimate details of how these technologies work, as they are explained fully in a white paper that is available for download from the Core Store. Instead, we will focus on the application of this technology in design reviews. When used prior to tape out, Chip DNA Analysis is a powerful tool that can be employed to catch mistakes and prevent headaches.
Let us begin with looking at the kind of information that is available to an IP manager in a Chip DNA report:
- A list of all of the IP that was detected in the SoC
- An indication of the version(s) of the IP that was detected
- Whether all the files associated with the IP are present
- Whether any of the files have been modified
Having this kind of information provides the IP manager with the capability to ask some very important questions prior to tape out to make sure that the engineering team, the legal team, and the finance team are all on the same page. The example below shows how checklists based on DNA reports can be used in this fashion.
In this example, the checklist shows that nine third-party IP blocks were detected during the course of the Chip DNA Analysis process. For each of these IPs, simple questions are asked:
Is the IP expected?
Sometimes IP reuse is done by copying one chip design database to the next, including the third-party IP. In this example, IP7 was detected, but upon review it was discovered that the design spec for the SoC had changed, but that the design database did not remove the IP. The action that would be taken to resolve this issue would be to remove the IP and rerun Chip DNA Analysis to confirm that it has been completely removed.
Is the contract in place with the supplier?
This issue can arise when chip design databases are copied from one SoC to the next. In the example here, the contract for IP4 is not in place and actions need to be taken quickly to ensure that a new license is completed before tape out.
Is the latest version present?
Oftentimes, we get calls from our customers asking us to confirm that they have the latest version of the IP before tapeout. Of course, with our Xena IP management system, customers always have access to the latest version of our IP automatically, but for many IP suppliers that use more primitive methods for IP distribution, customers can miss notifications of new versions.
In this example, IP3 was found to be at version 1.2, when version 1.5 was available. A decision was made to upgrade to the latest version before tapeout.
Are all the files that are expected actually present?
This kind of check is important to verify that the all of the IP that is expected is present and not modified in any way that was not intended. Such checks are important to ensure that all modifications are understood and approved by the SoC design team.
In this example, IP1 was purposely modified to remove a feature that was not needed, but IP9 was modified to remove a header that contained important tracking information. Since it was modified, the Chip DNA Analysis software reports it as “missing.” After review, the team decided to restore all of the files to IP9 to preserve the tracking information.
Are there any extra files present in the design?
A growing concern in semiconductors is the insertion of malicious code—such as a Trojan horse, malware, backdoor, or similar—into the hardware that can then be activated in a system long after the design process is completed. The Chip DNA Analysis report can show that there are files that were detected in the SoC that are associated with the IP, but that were not put there by the IP owner. This is critically important in projects where contractors and subcontractors are handling the code, such as in the case of many government, military, and aeronautics projects. In this example, no extra files were detected.
What does this mean for my company?
Fingerprinting is a new and exciting technology that gives semiconductor companies a powerful tool to deal with the huge volume of IP that they are using in their SoC designs today. Using Chip DNA Analysis as a standard part of IP design reviews is just one of many applications we expect to see that will benefit not only the IP user, but also the IP buyer.
IP providers from around the world are joining the Core Store ecosystem to add their products and associated IP Fingerprints to this centralized repository. To learn more about IP Fingerprinting and Chip DNA Analysis, please visit https://the-core-store.com.